1. Field of the Invention
The invention relates to a shift register, and more particularly to a shift register array of a liquid crystal display apparatus.
2. Description of the Related Art
At present, gate drivers and source drivers of most of the liquid crystal displays are disposed outside of the liquid crystal display panels, and are configured to generate gate pulse signals and data signals, respectively. However, using gate drivers increases costs. In order to reduce costs, the shift register arrays, which function as gate drivers, are fabricated on a glass substrate, i.e. an integrated driving circuit. An amorphous thin film transistor (TFT) process is often used in an active matrix liquid crystal display (AMLCD). Therefore, given the above, for an AMLCD panel, the panel may abnormally operate due to stress problems of the shift registers after the panel is illuminated.
FIG. 1 shows a circuit diagram of a conventional shift register. In FIG. 1, only a single shift register 100 is shown. A plurality of shift registers 100 can form a shift register array, which functions as a gate driver. As shown in FIG. 1, the shift register 100 comprises a transistor 101, a transistor 102, a pull-up unit 110, a pull-down unit 120 and a transistor 106. The transistor 101 is coupled to a node N10 and receives a gate pulse signal GateN−1 output from a previous stage shift register. The transistor 102 receives a clock signal CK and outputs a gate pulse signal GateN of the shift register 100 according a voltage of the node N10. The pull-down unit 120 is coupled between the transistor 102 and a ground VSS. The pull-up unit 110 is coupled between the node N10 and the ground VSS and comprises three transistors 103-105. The transistor 103 is coupled between the node N10 and the ground VSS and has a gate coupled to a node N11. The transistor 104 is coupled between the node N11 and a power VDD and has a gate coupled to the power VDD such that a diode-connected transistor 104 is formed. The transistor 105 is coupled between the node N11 and the ground VSS and has a gate coupled to the node N10. Hence, the transistors 104 and 105 can form a dynamic inverter.
Furthermore, the transistor 106 is coupled between the node N10 and the ground VSS and has a gate for receiving a gate pulse signal GateN+1 output from a next stage shift register. However, for the shift register 100, it does not matter if the gate pulse signal GateN−1 or the clock signal CK are active or not, the transistor 104 will always be turned on, thus shortening operating lifespan of the transistor 104 and possibly causing damage.